1. Field of the Invention
The present invention relates to phase-locked loop (PLL) clocking circuits in general and in particular to a PLL clock circuit capable of adjusting its frequency to lock onto either of two sources with a minimum of disturbance to the phase of its output clock signal.
2. Related Art
In telephony systems it is often required to have the local clock follow a primary master clock provided by a larger, often remote, network. For example, in U.S. Pat. No. 4,519,071 for Phase-Locked Loop and Clock Circuit For A Line Switch, issued May 21, 1985 to Miller, a phase-locked loop circuit permits clock signals which are generated in a line switch module to be in phase synchronism with any one of a number of PCM lines. A processor is provided to control clock generation and to select which of the PCM lines is used to provide clock signals.
In U.S. Pat. No. 3,936,604 entitled Synchronization Of Clocks in Digitial Signalling Networks, issued Feb. 3, 1976 to Pommerening, a station scans all available clock signals, its own and all those derived from the incoming data signals, compares the scanned signals one by one with its own operating rate, and adjusts the rate to conform to the slowest signal.
In certain telephony system, where reliability requirements are high, it is necessary to provide dual, redundant, system components. For example, in Northern Telecom's DV-1 system, where voice and data signals are transferred over a synchronous system bus, it is necessary to provide dual processors; a primary processor and a back-up processor. The primary processor must adjust its clock to maintain synchronism with the larger telephony network, while the back-up processor must tighly lock to and track the primary processor clock in order to be able to become the active processor without disrupting the system operation should the primary processor for any reason loose sanity or become disabled. For reasons of economy, it is desirable that the PLL circuits in both primary and back-up processors be identical.